
module AttackTable(
  input  wire        clk,
  input  wire        rst_n,
  input  wire [6:0]  addr,
  output reg  [6:0]  data
);

always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
	data <= #1 7'b0;
    else
	case(addr)
        7'h00: data <= #1 7'b0000000;
        7'h01: data <= #1 7'b0000000;
        7'h02: data <= #1 7'b0000000;
        7'h03: data <= #1 7'b0000000;
        7'h04: data <= #1 7'b0000000;
        7'h05: data <= #1 7'b0000001;
        7'h06: data <= #1 7'b0000001;
        7'h07: data <= #1 7'b0000001;
        7'h08: data <= #1 7'b0000001;
        7'h09: data <= #1 7'b0000001;
        7'h0a: data <= #1 7'b0000010;
        7'h0b: data <= #1 7'b0000010;
        7'h0c: data <= #1 7'b0000010;
        7'h0d: data <= #1 7'b0000010;
        7'h0e: data <= #1 7'b0000011;
        7'h0f: data <= #1 7'b0000011;
        7'h10: data <= #1 7'b0000011;
        7'h11: data <= #1 7'b0000011;
        7'h12: data <= #1 7'b0000100;
        7'h13: data <= #1 7'b0000100;
        7'h14: data <= #1 7'b0000100;
        7'h15: data <= #1 7'b0000100;
        7'h16: data <= #1 7'b0000100;
        7'h17: data <= #1 7'b0000101;
        7'h18: data <= #1 7'b0000101;
        7'h19: data <= #1 7'b0000101;
        7'h1a: data <= #1 7'b0000110;
        7'h1b: data <= #1 7'b0000110;
        7'h1c: data <= #1 7'b0000110;
        7'h1d: data <= #1 7'b0000110;
        7'h1e: data <= #1 7'b0000111;
        7'h1f: data <= #1 7'b0000111;
        7'h20: data <= #1 7'b0000111;
        7'h21: data <= #1 7'b0000111;
        7'h22: data <= #1 7'b0001000;
        7'h23: data <= #1 7'b0001000;
        7'h24: data <= #1 7'b0001000;
        7'h25: data <= #1 7'b0001001;
        7'h26: data <= #1 7'b0001001;
        7'h27: data <= #1 7'b0001001;
        7'h28: data <= #1 7'b0001001;
        7'h29: data <= #1 7'b0001010;
        7'h2a: data <= #1 7'b0001010;
        7'h2b: data <= #1 7'b0001010;
        7'h2c: data <= #1 7'b0001011;
        7'h2d: data <= #1 7'b0001011;
        7'h2e: data <= #1 7'b0001011;
        7'h2f: data <= #1 7'b0001100;
        7'h30: data <= #1 7'b0001100;
        7'h31: data <= #1 7'b0001100;
        7'h32: data <= #1 7'b0001101;
        7'h33: data <= #1 7'b0001101;
        7'h34: data <= #1 7'b0001101;
        7'h35: data <= #1 7'b0001110;
        7'h36: data <= #1 7'b0001110;
        7'h37: data <= #1 7'b0001110;
        7'h38: data <= #1 7'b0001111;
        7'h39: data <= #1 7'b0001111;
        7'h3a: data <= #1 7'b0001111;
        7'h3b: data <= #1 7'b0010000;
        7'h3c: data <= #1 7'b0010000;
        7'h3d: data <= #1 7'b0010001;
        7'h3e: data <= #1 7'b0010001;
        7'h3f: data <= #1 7'b0010001;
        7'h40: data <= #1 7'b0010010;
        7'h41: data <= #1 7'b0010010;
        7'h42: data <= #1 7'b0010011;
        7'h43: data <= #1 7'b0010011;
        7'h44: data <= #1 7'b0010100;
        7'h45: data <= #1 7'b0010100;
        7'h46: data <= #1 7'b0010101;
        7'h47: data <= #1 7'b0010101;
        7'h48: data <= #1 7'b0010101;
        7'h49: data <= #1 7'b0010110;
        7'h4a: data <= #1 7'b0010110;
        7'h4b: data <= #1 7'b0010111;
        7'h4c: data <= #1 7'b0010111;
        7'h4d: data <= #1 7'b0011000;
        7'h4e: data <= #1 7'b0011000;
        7'h4f: data <= #1 7'b0011001;
        7'h50: data <= #1 7'b0011010;
        7'h51: data <= #1 7'b0011010;
        7'h52: data <= #1 7'b0011011;
        7'h53: data <= #1 7'b0011011;
        7'h54: data <= #1 7'b0011100;
        7'h55: data <= #1 7'b0011101;
        7'h56: data <= #1 7'b0011101;
        7'h57: data <= #1 7'b0011110;
        7'h58: data <= #1 7'b0011110;
        7'h59: data <= #1 7'b0011111;
        7'h5a: data <= #1 7'b0100000;
        7'h5b: data <= #1 7'b0100001;
        7'h5c: data <= #1 7'b0100001;
        7'h5d: data <= #1 7'b0100010;
        7'h5e: data <= #1 7'b0100011;
        7'h5f: data <= #1 7'b0100100;
        7'h60: data <= #1 7'b0100100;
        7'h61: data <= #1 7'b0100101;
        7'h62: data <= #1 7'b0100110;
        7'h63: data <= #1 7'b0100111;
        7'h64: data <= #1 7'b0101000;
        7'h65: data <= #1 7'b0101001;
        7'h66: data <= #1 7'b0101010;
        7'h67: data <= #1 7'b0101011;
        7'h68: data <= #1 7'b0101100;
        7'h69: data <= #1 7'b0101101;
        7'h6a: data <= #1 7'b0101111;
        7'h6b: data <= #1 7'b0110000;
        7'h6c: data <= #1 7'b0110001;
        7'h6d: data <= #1 7'b0110011;
        7'h6e: data <= #1 7'b0110100;
        7'h6f: data <= #1 7'b0110110;
        7'h70: data <= #1 7'b0111000;
        7'h71: data <= #1 7'b0111001;
        7'h72: data <= #1 7'b0111011;
        7'h73: data <= #1 7'b0111101;
        7'h74: data <= #1 7'b1000000;
        7'h75: data <= #1 7'b1000010;
        7'h76: data <= #1 7'b1000101;
        7'h77: data <= #1 7'b1001000;
        7'h78: data <= #1 7'b1001011;
        7'h79: data <= #1 7'b1010000;
        7'h7a: data <= #1 7'b1010100;
        7'h7b: data <= #1 7'b1011010;
        7'h7c: data <= #1 7'b1101100;
        7'h7d: data <= #1 7'b1111111;
        7'h7f: data <= #1 7'b1111111;
        endcase		
end

endmodule
